The present invention generally relates to the implementation of circuit designs, and more particularly to reusing selected portions of a prior circuit implementation to implement portions of a new circuit design.
The term xe2x80x9cnetxe2x80x9d as used herein refers to a conductive region connecting components of a user""s circuit design. For example, one net may connect the output terminal of an AND gate to the input. terminal of another AND gate and to the input terminal of a flip-flop. An AND gate is one component type, and a flip-flop is another component type. An xe2x80x9cinstancexe2x80x9d is a single occurrence of a component type. A xe2x80x9cnetlistxe2x80x9d is a list of all the nets that connect the component instances of a user""s design and the component instances connected by each net.
The circuit design process generally includes, in order, design entry, synthesis, optimization, device mapping, and place-and-route, along with functional and timing simulations to verify correctness. If an error is identified late in the process, much of the process may need to be repeated in order to integrate a design change.
One solution to avoid repeating the entire process of optimization, device mapping, and place-and-route is to only re-implement the parts of the design that changed from the previous design cycle. Although this solution may be fairly straightforward when using schematics for design entry (because changes to a schematic cause very little change in a netlist), it is more difficult when the design has been generated through the use of high-level languages and synthesis. That is, a small design change in a high-level language may substantially impact the entire design process, and the new implementation may no longer meet the designer""s timing requirements, fit the target device, or have the same pin assignments as the prior implementation. Thus, additional work may be required to address the problems that were introduced by a small design change. It is desirable that significantly different implementations do not result from relatively small design changes, so that additional engineering costs are not incurred. An incremental design method that addresses the aforementioned problems, as well as other related problems, is therefore desirable.
The present invention generally relates to the implementation of circuit designs, and more particularly to testing for logical equivalence between portions of a new circuit design and portions of a prior circuit implementation and reusing selected portions of the prior circuit implementation to implement the new circuit design. By testing for logical equivalence instead of testing for structural equivalence, the present invention eliminates unnecessary repetition of stages of the design cycle such as optimization, device mapping, and place-and-route.
In various embodiments, the invention generally includes comparing for logical equivalence primary outputs of the new design to corresponding primary outputs of a prior implementation. If the logic is equivalent, the implementation of the primary outputs from the prior implementation is reused to implement the corresponding primary outputs of the new design.
In another embodiment, attributes can be associated with the primary outputs of the new design to selectively control whether elements of the prior implementation are used to implement the primary outputs. Thus, a designer has control over which portions of a new design are to be implemented without regard to the prior implementation.
For outputs in the new design that are not present in the prior implementation and for outputs in the new design having logic that has changed from the prior implementation, the primary outputs of the new design are expressed in terms of the logic from the prior implementation, thereby reusing portions of the prior implementation for the new and changed primary outputs.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims which follow.